This invention relates generally to serial-to-parallel converters, and more particularly to a multiple time domain serial-to-parallel converter for processing traffic within a telecommunications system.
Telecommunications systems include customer premise equipment (CPE), local loops connecting each customer premises to a central office or other node, the nodes providing switching and signaling for the system, and internode trunks connecting the various nodes. The customer premise equipment (CPE) includes telephones, modems for communicating data over phone lines, and computer and other devices that can directly communicate video, audio, and other data over a data link. The network nodes include traditional circuit-switched nodes that have transmission paths dedicated to specific users for the duration of a call and employ continuous, fixed-bandwidth transmission and packet-switch nodes that allow dynamic bandwidths, dependent on the application. The transmission media between nodes may be wireline or wireless.
One type of wireline transmission media is optical fiber which is a thin strand of glass that is designed to carry information using pulses of light. Separate optical fibers are bundled together and encased in an outer sheath to form fiber cables. Optical fiber provides users with higher reliability, superior performance, and greater flexibility than traditional copper-based systems.
Optical transmission facilities are installed in the form of synchronous optical network (SONET) rings. SONET defines a line rate hierarchy and frame format as described by the American National Standards Institute (ANSI) T1.105 and T1.106 specifications. Nodes on a SONET ring provide add-drop multiplexing and digital cross-connect functionality for traffic on the ring. SONET rings are typically bi-directional to provide redundant transmission paths and protection in case of a line or node failure.
SONET traffic is serially transmitted around a SONET ring. When received at a node, SONET traffic is converted into parallel data. Thereafter, the parallel data is synchronized to the internal clock of the node for processing. Typically, serial data is converted to parallel data within the transmission time domain. As a result, each stream of parallel data feeds forward the clock signal of the transmission time domain and must be individually synchronized to the local time domain. This is commonly performed with a first-in-first-out (FIFO) circuit which requires the use of memory modules and other resources to synchronize the data from the transmission time domain to the internal time domain of the node.
The present invention provides a multiple time domain serial-to-parallel converter that substantially eliminates or reduces the problems and disadvantages associated with previous methods and systems. In particular, the multiple time domain serial-to-parallel converter converts serial traffic in a transmission or other first time domain into parallel traffic in an internal or other second time domain.
In accordance with one embodiment of the present invention, a multiple time domain serial-to-parallel converter includes a combiner operable to receive a stream of serial data within a first time domain and to accumulate a portion of the serial data into a set of parallel data. A first hold register is coupled to the combiner. The first hold register is configured to operate within the first time domain and operable to load the set of parallel data in response to a first load signal based on the first time domain. A second hold register is coupled to the first hold register. The second hold register is configured to operate within a second time domain and operable to load the set of parallel data from the first hold register in response to a second load signal based on the second time domain.
More specifically, in accordance with a particular embodiment of the present invention, the first time domain may be a transmission clock recovered with the stream of serial data at a network element. The second time domain may be an internal clock for the network element. In this and other embodiments, the first hold register, the second hold register, and the accumulator may each be implemented in an application specific integrated circuit (ASIC) with a series of flip-flops and multiplexers.
The multiple time domain serial-to-parallel converter may also include a retimer and an enabler. In this embodiment, the retimer is operable to generate the second load signal by retiming the first load signal from the first time domain into the second time domain. This may be accomplished by delaying the first load signal until an active edge of a clock signal for the second time domain. The enabler enables downstream use of the set of parallel data from the second hold register based on a delay of the second load signal. The retimer and enabler may be implemented with flip-flops in the application specific integrated circuit (ASIC).
Technical advantages of the present invention include providing an improved method and system for converting serial traffic to parallel traffic in a network element or other suitable device. In particular, the multiple time domain serial-to-parallel converter simultaneously converts serial traffic received at a network element in a transmission time domain into parallel traffic in an internal time domain of the network element. As a result, incoming data streams are each efficiently synchronized to the internal clock and each feed forward the internal clock. In addition, the method and system utilize a streamlined memory module that requires no random access memory (RAM) and is self-contained. Accordingly, equipment and resource use is reduced within the network element. This allows network elements to be constructed at lower costs and to be operated more efficiently.
Other technical advantages of the present invention will be readily apparent to one skilled in the art from the following figures, description, and claims.